IEE5650: VLSI Testing

Assignment #0  (Due: Mar. 3, 2015)

last update: Feb. 23,2015

Reading:

• Podem source codes
• Benchmark circuits
• Email following two parts to TA ( genius548@gmail.com )with the title "[VLSI_Testing]xxxxxxx" (student number)
1. Whole modified program. Adding comment "modified hw" to modified lines of code. Remember to compress the source code into zip format or tgz format
2. Report. Briefly describe your method to accomplish the assignment. How to use your program (what kind of command to give). What kind of outcome for the specific circuit (one or two examples only)
3. (Optional) Suggestions
• Naming and characteristics of benchmark circuits (decompressed from circuits.tgz):
  (In the following, XXX is the identification number of the circuit, e.g., "27" is the identification number of s27.bench)
  • sXXX_seq.bench is the original ISCAS89 circuits.
    If you need combinational parts of these circuits , you can simply take the PPIs as PIs, and all PPOs as POs in your codes.
  • sXXX_opt.bench is the combinational parts of sXXX_seq.bench optimized with the Synopsys DC.
  • sXXX_com.bench is the same as sXXX_opt.bench. (We do not need these circuits at all.)
  • cXXX.bench is the combinational ISCAS85 circuits.

Homework Problems:

(100 pts) Get yourself familiar with the data structure of the podem test generation package (though we do not use the test generation parts yet). Please use the circuit parser to read benchmark circuits and then output the following attributes of the circuits. Choose benchmark circuits according to different criteria including combinational or sequential, optimized or non-optimized, larger or small circuits etc.

• Number of inputs
• Number of outputs
• Total number of gates including inverter, or, nor, and, nand
• Number of gates in each type
• Nuber of flip-flops(if available)
• Total number of signal nets.
  A net is any wire connecting between (PI, PPI, gate outputs) to (PO, PPO and gate inputs). Note that a gate connecting to different gates will be counted as different nets. For example, the output of gate A is branched to both gate C and D. As a result, there are two branch nets: A->C and A->D, and one stem net A.
• Number of branch nets
• Number of stem nets
• Average number of fanouts of each gate(all kind of gates)