IEE5650 VLSI Testing

Schedule


Week

Monday - CDX EDB06 (3hr)

1

2/13

1. Course overview

2. Introduction to data structures of a gate-level netlist parser

3. Introduction

 

Assignment 0

2

2/20

1. Introduction

2. Logic Simulation

 

Assignment 1

3

2/27*

4

3/6

1. Logic Simulation

2. Fault Modeling

 

Assignment 2

5

3/13

1. Fault Modeling

2. Fault Simulation

 

Assignment 3

6

3/20

1. Fault Simulation

2. Comb_ATPG

7

3/27

1. Comb_ATPG

 

Assignment 4

8

4/3*

9

4/10

Midterm

10

4/17

1. Testability

2. seq_ATPG

 

Assignment 5

11

4/24

1. Testability

2. seq_ATPG

3. DFT

12

5/1

1. seq_ATPG

2. DFT

 

Assignment 6

13

5/8

1. DFT

2.BIST

14

5/15

1. Lab1

2. Lab2

15

5/22

1.BIST

2.Test Compression

16

5/29*

17

6/5

1.Test Compression

2.memory testing

18

6/12

Final Examination