IEE5650: VLSI Testing

Assignment #5   (Due: May. 29, 2020)

Last update: May. 13, 2020


Reading:

Homework Problems:

  1. (150 pts) Fault Simulation
    1. (20 pts) Please generate patterns by PODEM, and then run PODEM using the patterns and the "fault simulation only" option to obtain the fault coverages. Also, please compare the fault coverage reported by the original PODEM program and one based on checkpoint theorem (implemented in the homework #4).
      Note that you don't need to translate the results of checkpoint faults back to the original full fault list (without collapsing).
    2. (30 pts) The fault simulator implemented in the package uses parallel fault simulation algorithm which simulates 16 faults per pass by default. Modify the fault simulation routine to simulate more and less faults per pass, say 4, 8, 32, 64, etc. Fault simulator should report the same fault coverage for all these cases.
      Give a table comparing the CPU runtimes under different fault numbers. Show each speed-up with respect to the case of simulating just one fault per pass. Use random patterns for fault simulation in your comparison (randomly generate one million patterns).
    3. (100 pts) Please implement a parallel fault simulator for the bridging fault model described in homework #4.

Grading:

Attention:

  1. Use the command to generate patterns for a circuit by running built-in ATPG:

    ./atpg -output [output_pattern_file] [circuit_name]

  2. You need to create a new command for 1.(c):

    ./atpg -bridging_fsim -input [input_pattern_file] [circuit_name]