|
Week |
Tuesday - CDX
ED022 (3hr)
|
|
|
1 |
2/23 |
1. Course overview 2. Introduction to data structures of a gate-level netlist parser |
|
2 |
3/2 |
Introduction
to test process |
|
3 |
3/9 |
1. Introduction to test process 2.Logic Simulation Assignment 1 |
|
4 |
3/16 |
1. Logic Simulation 2. Fault Modeling Assignment 2 |
|
5 |
3/23 |
1. Fault Modeling
2. Fault Simulation Assignment 3 |
|
6 |
3/30 |
WAT
|
|
7 |
4/6 |
1. Fault Simulation 2. Combinational Test
Generation
Assignment 4
|
|
8 |
4/13 |
Combinational Test Generation Assignment 5
|
|
9 |
4/20 |
Combinational
Test Generation |
|
10 |
4/27 |
Midterm |
|
11 |
5/4 |
1. Testability Analysis 2. Sequential
Test Generation
Assignment 6 |
|
12 |
5/11 |
Sequential Test Generation |
|
13 |
5/18 |
Design
for Testability |
|
14 |
5/25 |
Lab
Scan-Chain Insertion - 1
Lab 2 Scan-Chain Insertion - 2 account Lab2 hw |
|
15 |
6/1 |
Assignment 7
|
|
16 |
6/8 |
Built-in
Self-Test |
|
17 |
6/15 |
1. Memory Testing
2. Boundary Scan |
|
18 |
6/22 |
Final Examination |