IEE5650 VLSI Testing

Schedule


Week

Monday - CDX ED301 (3hr)

1

2/26

1. Course overview

2. Introduction to data structures of a gate-level netlist parser

 

Assignment 0

2

3/5

1. Introduction

 

Assignment 1

3

3/12

1. Introduction

2. Logic Simulation

4

3/19

Logic Simulation

 

Assignment 2

5

3/26

1. Logic Simulation

2. Fault Modeling

 

Assignment 3

6

4/2

1. Fault Modeling

2. Fault Simulation

7

4/9

1. Fault Simulation

2. Comb_ATPG

 

Assignment 4

8

4/16

Comb_ATPG

9

4/23

Midterm

10

4/30

1. Testability

2. Seq_ATPG

 

Assignment 5

11

5/7

1. Testability

2. Seq_ATPG

12

5/14

1. Seq_ATPG

2. DFT

 

Assignment 6

13

5/21

1. DFT

2. BIST

14

5/28

Lab1

Lab2

15

6/4

1. BIST

2. Test Compression

16

6/11

Final Exam

17

6/18*