EEIE30069 VLSI Testing and Design for Testability

Schedule


Week

Thursday 15:30~18:20 (R789) - Online Class

1

9/15

1. Honor code

2. Course overview

3. Introduction to data structures

of a gate-level netlist parser

Assignment 0

TA: Yu-Teng Nien

2

9/22

Introduction to Test Process

Assignment 1

TA: Vivian Wu

3

9/29

1. Introduction to Test Process

2. Logic Simulation

4

10/6

1. Logic Simulation

2. Fault Modeling

Assignment 2

TA: Yu-Teng Nien

5

10/13

1. Fault Modeling

2. Fault Simulation

Assignment 3

TA: Vivian Wu

6

10/20

Fault Simulation

7

10/27

Comb ATPG

Assignment 4

TA: Yu-Teng Nien

8

11/3

Midterm at EDB27

9

11/10

Comb ATPG

10

11/17

Testability Analysis

Assignment 5

TA: Vivian Wu

11

11/24

Seq ATPG

12

12/1

1. Seq ATPG

2. DFT

Assignment 6

TA: Yu-Teng Nien

13

12/8

1. DFT

2. BIST

14

12/15

1. Lab1

2. Lab2

Lab at ED415

15

12/22

Test Compression

16

12/29

Final Exam at EDB27

17

1/5

(Optional)

18

1/12

(Optional)