EEIE30069 VLSI Testing and Design for Testability

Schedule


Week

Monday 09:00~12:00 (M234) - Online Class

1

9/11

1. Honor code

2. Course overview

3. Introduction to data structures

of a gate-level netlist parser

Assignment 0

TA: Cheng-Xsiang Tsai

2

9/18

Introduction to Test Process

Assignment 1

TA: Cheng-Xsiang Tsai

3

9/25

1. Introduction to Test Process

2. Logic Simulation

4

10/2

1. Logic Simulation

2. Fault Modeling

Assignment 2

TA: Yung-Jheng Wang

5

10/9

National Day

6

10/16

1. Fault Modeling

2. Fault Simulation

Assignment 3

TA: Cheng-Xsiang Tsai

7

10/23

1. Fault Simulation

2. Comb ATPG

8

10/30

Comb ATPG

Assignment 4

TA: Yung-Jheng Wang

9

11/6

Midterm Exam at ED102

10

11/13

Testability Analysis

Assignment 5

TA: Cheng-Xsiang Tsai

11

11/20

Seq ATPG

12

11/27

1. Seq ATPG

2. DFT

Assignment 6

TA: Yung-Jheng Wang

13

12/4

1. DFT

2. BIST

14

12/11

Test Compression

15

12/18

1. Lab1

2. Lab2

Lab at ED415

16

12/25

Final Exam at ED102

17

1/1

New Year's Day

18

1/8

(Optional)