EEIE30069 VLSI Testing and Design for Testability

Schedule


Week

Monday 09:00~12:00 (M234) - Online Class

1

9/2

1. Honor code

2. Course overview

3. Introduction to data structures

of a gate-level netlist parser

Assignment 0

TA: Ho-Jie Hsu

2

9/9

Introduction to Test Process

Assignment 1

TA: Ho-Jie Hsu

3

9/16

1. Introduction to Test Process

2. Logic Simulation

4

9/23

1. Logic Simulation

2. Fault Modeling

Assignment 2

TA: Ting-Wei Chen

5

9/30

1. Fault Modeling

2. Fault Simulation

Assignment 3

TA: Ho-Jie Hsu

6

10/7

1. Fault Simulation

2. Comb ATPG

7

10/14

1. Comb ATPG

Assignment 4

TA: Ting-Wei Chen

8

10/21

Midterm Exam at EDB06

9

10/28

Comb ATPG

Assignment 5

TA: Ho-Jie Hsu

10

11/4

Testability Analysis

11

11/11

Seq ATPG

Assignment 6

TA: Ting-Wei Chen

12

11/18

1. Seq ATPG

2. DFT

13

11/25

1. DFT

2. BIST

14

12/2

Test Compression

15

12/9

1. Lab1

2. Lab2

Lab at ED415

16

12/16

Final Exam at ED301

17

12/23

(Optional)

18

12/30

(Optional)