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2023

Chin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao“Outlier Detection for Analog Tests Using Deep Learning Techniques,” VLSI Test Symposium (VTS), 2023

Yu-Teng Nien, Chen-Hong Li, Pei-Yin Wu, Yung-Jheng Wang, Kai-Chiang Wu, Mango C.-T. Chao“Test Generation for Defect-Based Faults of Scan Flip-Flops,” VLSI Test Symposium (VTS), 2023

2022

Dong-Zhen Lee, Ying-Yen Chen, Kai-Chiang Wu, Mango C.-T. Chao, “Improving Cell-Aware Test for Intra-Cell Short Defects,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022

Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, Mango C.-T. Chao, “A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction,” International Symposium on Physical Design (ISPD), 2022

Li-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang, “Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs,” International Symposium on Quality Electronic Design (ISQED), 2022

Shuo-Wen Chang, Yu-Teng Nien, Yu-Pang Hu, Kai-Chiang Wu, Chi-Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao, “Test Methodology for Defect-Based Bridge Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2022

Ho-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu and Mango C.-T. Chao, “Rule Generation for Classifying SLT Failed Parts”, IEEE VLSI Test Symposium (VTS), 2022

2021

Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao, “Methodology of Generating Timing-Slack-Based Cell-Aware Tests,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021

Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao, “Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks,” IEEE 39th VLSI Test Symposium (VTS), 2021

2020

Wen-Hsiang Chang, Li-Yi Lin, Yu-Guang Chen, Mango C.-T. Chao, “Power Distribution Network Generation for Optimizing IR-Drop Aware Timing,” IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020

Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, Mango Chao, “Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network,” International Symposium on Physical Design (ISPD), 2020

Yu-Pang Hu, Shuo-Wen Chang, Kai-Chiang Wu, Chi Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao, “Test Methodology for Defect-based Bridge Faults,” IEEE International Test Conference in Asia (ITC-Asia), 2020

Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao, “CNN-based Stochastic Regression for IDDQ Outlier Identification,” IEEE 38th VLSI Test Symposium (VTS), 2020

2019

Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, and Mango C.-T. Chao, “Methodology of Generating Timing-Slack-Based Cell-Aware Tests,” IEEE International Test Conference (ITC), 2019

Y.-Z. Wang, J. Wu, S.-H. Chen, Mango C.-T. Chao, and C.-H. Yang, “Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs,” IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2019

Tse-Wei Wu, Dong-Zhen Lee, Kai-Chiang Wu, Yu-Hao Huang, Ying-Yen Chen,Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao and Mango C.-T.Chao,“Layout-Based Dual-Cell-Aware Tests”, IEEE VLSI Test Symposium(VTS), 2019

2018

Chien-Hsueh Lin, Chih-Ying Tsai, Kao-Chi Lee, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee and Mango C.-T. Chao,“A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement”,IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD), 2018

Keng-Wei Chang, Chun-Yang Huang, Szu-Pang Mu, Jian-Min Huangy, Shi-Hao Cheny, Mango C.-T. Chao,“DVFS Binning Using Machine-Learning Techniques”,IEEE International Test Conference in Asia (ITC-Asia), 2018

2017

Wen-Hsiang Chang, Chien-Hsueh Lin, Szu-Pang Mu, Li-De Chen, Cheng-Hong Tsai, Yen-Chih Chiu, Mango C.-T. Chao,“Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique”,IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD), 2017

Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, and Mango C.-T. Chao, “Predicting Vt Variation and Static IR Drop of Ring Oscillators Using Model-Fitting Techniques”,IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2017

Yu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien, Ying-Yen Chen, Max Wu, Jih-Nung Lee, Mango C.-T. Chao, “Methodology of Generating Dual-Cell-Aware Tests”,IEEE VLSI Test Symposium (VTS), 2017, (Best paper award)

Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango C.-T. Chao, “Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators”,IEEE VLSI Test Symposium (VTS), 2017, (Best paper award nominee)

2016

Wen-Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu, Cheng-Hong Tsai, Yen-Chih Chiu, Mango C.-T. Chao,“Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique”,ACM/IEEE International Symposium on Physical Design (ISPD), 2016(Best paper award)

Szu-Pang Mu, Mango C.-T. Chao, Shi-Hao Chen, Yi-Ming Wang,“Statistical Framework and Built-in Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators”,IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2016

Shu-Yung Bin, Shih-Feng Lin, Ya-Ching Cheng, Wen-Rong Liau, Alex Hou, Mango C.-T. Chao,“Predicting Shot-Level SRAM Read/Write Margin based on Measured Transistor Characteristics”,IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2016

Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee and Mango C.-T. Chao,“Predicting Vt Mean and Variance from Parallel Id Measurement with Model-Fitting Technique”,IEEE VLSI Test Symposium (VTS), 2016

Szu-Pang Mu, Wen-Hsiang Chang, Mango C.-T. Chao, Yi-Ming Wang, Ming-Tung Chang, Min-Hsiu Tsai, “Statistical Methodology to Identify Optimal Placement of On-Chip Process Monitors for Predicting Fmax”,ACM/IEEE International Conference on Computer Aided Design (ICCAD), 2016

2015

Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango C.-T. Chao, “Random Pattern Generation for Post-Silicon Validation of DDR3 SDRAM”,IEEE VLSI Test Symposium (VTS), 2015

Hao-Yu Yang, Rei-Fu Huang, Chin-Lung Su, Kuan-Hong Lin, Hang-Kaung Shu, Chi-Wei Peng, Mango C.-T. Chao, “Testing Methods for Quaternary Content Addressable Memory Using Charge-Sharing Sensing Scheme”,IEEE International Test Conference (ITC), 2015

Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, Mango C.-T. Chao,“Statistical Techniques for Predicting System-Level Failure using Stress-Test Data”, IEEE VLSI Test Symposium (VTS), 2015

2014

Chen-Wei Lin, Mango C.-T. Chao, and Chih-Chieh Hsu, “A Novel Circuit-level Model for Gate Oxide Short and its Testing Method in SRAMs”,IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2014

Tseng-Chin Luo, Mango C.-T. Chao, Huan-Chi Tseng, Masaharu Goto, Philip A. Fisher, Yuan-Yao Chang, Chi-Min Chang, Takayuki Takao, Katsuhito Iwasaki, Cheng Mao Lee, “Fast Transistor Threshold Voltage Measurement Method for High-speed, High-accuracy Advanced Process Characterization”,IEEE Transactions on Very Large Scale Integration Systems (TVLSI),2014

Wen-Hsiang Chang, Mango C.-T. Chao, Shi-Hao Chen, “Practical Routability-Driven Design Flow for Multi-layer Power Networks Using Aluminum-Pad Layer”,IEEE Transactions on Very Large Scale Integration Systems (TVLSI),2014

Hao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango C.-T. Chao, Rei-Fu Huang,“Testing Methods for a Write-Assist Disturbance- Free Dual-Port SRAM”, IEEE VLSI Test Symposium (VTS), 2014 (Best paper nominee)

Yi-Ming Wang, Mango C.-T. Chao, Shi-Hao Chen, Hung-Chun Li, “Power-Switch Routing for Reducing Dynamic IR Drop in Multi-Domain MTCMOS Designs”, IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2014

2013

Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, and Mango C.-T. Chao, “Testing Retention Flip-flops in Power-gated Designs”,IEEE VLSI Test Symposium (VTS), 2013

Chen-Wei Lin, Chin-Yuan Huang, and Mango C.-T. Chao, “Testing of a Low-VMIN Data-Aware Dynamic-Supply 8T SRAM”,IEEE VLSI Test Symposium (VTS), 2013

Chen-Wei Lin, Mango C.-T. Chao, and Chih-Chieh Hsu, “Investigation of Gate Oxide Short in FinFETs and the Test Methods for FinFET SRAMs”,IEEE VLSI Test Symposium (VTS), 2013

Shi-Hao Chen, Youn-Long Lin, Mango C.-T. Chao, “Power-up Sequence Control for MTCMOS Designs”,IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2013

Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Chin-Yuan Huang, Mango C.-T. Chao, Rei-Fu Huang, “Fault Models and Test Methods for Subthreshold SRAMs”,IEEE Transactions on Computers (TC),2013

2012

Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango C.-T. Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, “Testing Strategies for a 9T Sub-threshold SRAM”, IEEE International Test Conference (ITC), 2012

Rei-Fu Huangy, Hao-Yu Yang, Mango C.-T. Chao, Shih-Chin Lin, “Alternate Hammering Test for Application-Specific DRAMs and an Industrial Case Study”,ACM/IEEE Design Automation Conference (DAC), 2012

Yi-Ming Wang, Shi-Hao Chen, Mango C.-T. Chao, “An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs”, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC-12), 2012

Tseng-Chin Luo, Mango C.-T. Chao, Philip A. Fisher, Chun-Ren Kuo, “A Novel Design Flow for Dummy Fill Using Boolean Mask Operations”,IEEE Transactions on Semiconductor Manufacturing (regular paper) (EI/SCI),2012

Hao-Yu Yang, Chi-Min Chang, Mango C.-T. Chao, Rei-Fu Huang, and Shih-Chin Lin, “Testing Methodology of Embedded DRAMs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2012

Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango C.-T. Chao, "Fault Models and Test Algorithm for a 9T Sub-threshold SRAM" , VLSI Test Technology Workshop, 2012

2011

Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, and Mango C.-T. Chao, “Detecting Stability Faults in Sub-threshold SRAMs”,ACM/IEEE International Conference on Computer Aided Design (ICCAD), 2011

Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango C.-T. Chao, Jing-Yang Jou, and Sonair Chen, “Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing”,IEEE International Test Conference (ITC), 2011

Tseng-Chin Luo, Mango C.-T. Chao, Michael S.-Y. Wu, Kuo-Tsai Li, Chin. C. Hsia, Huan-Chi Tseng, Philip A. Fisher, “A novel array-based test methodology for local process variation monitoring”,IEEE Transactions on Semiconductor Manufacturing(EI/SCI),2011

Chen-Wei Lin, Mango C.-T. Chao, and Yen-Shih Huang, “A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs”,IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2011

Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango C.-T. Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai, “Detecting Stuck-open Power Switches Using Delay Difference in Coarse-Grain MTCMOS Designs” , VLSI Design/CAD Symposium, 2011

2010

Szu-Pang Mu, Mango C.-T. Chao, “Theoretical Analysis for Low-Power Test Decompression Using Test-Slice Duplication”, IEEE VLSI Test Symposium (VTS), 2010

Mango C.-T. Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, “A Novel Test Flow for One-Time-Programming Applications of NROM Technology” ,IEEE Transactions on Very Large Scale Integration Systems(TVLSI), 2010

Yu-Ze Wu, Mango Chia-Tso Chao, “Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes”, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2010

Chien-Pang Lu, Mango C.-T. Chao, Chen-Hsing Lo, Chih-Wei Chang, “A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations”, IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD), 2010

Tseng-Chin Luo, Eric Leong, Mango C.-T. Chao, Philip A. Fisher, and Wen-Hsiang Chang, “Mask versus Schematic – An Enhanced Design-Verification Flow for First Silicon Success”, IEEE International Test Conference (ITC), 2010

Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango C.-T. Chao, and Rei-Fu Huang, “Fault Models and Test Methods for Subthreshold SRAMs”, IEEE International Test Conference (ITC), 2010

Mango C.-T. Chao, Ching-Yu Chin, Chen-Wei Lin, “Mathematical Yield Estimation for Two-Dimensional-Redundancy Memory Arrays”, ACM/IEEE International Conference on Computer Aided Design (ICCAD), 2010

Szu-Pang Mu, Willy Wang, Hao-Yu Yang, Mango C.-T. Chao, Shi-Hao Chen, Cheng-Hong Tsai, Chih-Mou Tseng, “Testing Methods for Detecting Stuck-open Power Switches in Coarse-Grain MTCMOS Designs”,ACM/IEEE International Conference on Computer Aided Design (ICCAD), 2010

2009

Tsun-Ming Tseng, Mango C.-T. Chao, Chien-Pang Lu, Chen-Hsing Lo, “Power-Switch Routing for Coarse-Grain MTCMOS Technologies”, ACM/IEEE International Conference on Computer Aided Design (ICCAD), 2009

Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango C.-T. Chao, “A Novel Test Flow for One-Time-Programming Applications of NROM Technology”, IEEE International Test Conference (ITC), 2009

Tseng-Chin Luo, Mango C.-T. Chao, Michael S.-Y. Wu, Kuo-Tsai Li, Chin. C. Hsia, Huan-Chi Tseng, Chuen-Uan Huang, Yuan-Yao Chang, Samuel C. Pan, Konrad K.-L. Young, “A novel array-based test methodology for local process variation monitoring”, IEEE International Test Conference (ITC), 2009

Meng-Jai Tasi, Mango C.-T. Chao, Jing-Yang Jou, Meng-Chen Wu, “Multiple-Fault Diagnosis Using Faulty-Region Identification”, IEEE VLSI Test Symposium (VTS), 2009

2008

2007

2006

Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng, “Coverage Loss by Using Space Compactors in Presence of Unknown Values”, ACM/IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), 2006

2005

Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng, “ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values”, IEEE International Conference on Computer Design (ICCD), pp. 147-152, 2005

Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng, “Response Shaper: A Novel Technique To Enhance Unknown Tolerance for Output Response Compaction”, ACM/IEEE International Conference on Computer Aided Design (ICCAD), pp. 80-87, 2005

2004

Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang, “A clustering- and probability-based approach for time-multiplexed FPGA partitioning”, in Integration: The VLSI Journal, Vol. 38, Issue 2, pp. 245-265, December 2004

Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng, “Static Statistical Timing Analysis for Latch-Based Pipeline Designs”, ACM/IEEE International Conference on Computer Aided Design (ICCAD), pp. 469-472, 2004

Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng, “Pattern Selection for Testing of Deep Sub-Micron Timing Defects”, ACM/IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1060-1065 Vol.2, 2004

2001

Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, and Yao-Wen Chang, “Generic ILP-based Approaches for Time-multiplexed FPGA Partitioning”, IEEE International Conference on Computer Design (ICCD), pp. 335-347, 2001

1999

Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang, “A Clustering- and Probability-based Approach for Time- multiplexed FPGA”, ACM/IEEE International Conference on Computer Aided Design (ICCAD), pp 364-369, 1999