IEE5650 VLSI Testing

Schedule


Week

Monday - CDX ED201 (3hr)

1

2/22

1. Course overview

2. Introduction to data structures of a gate-level netlist parser

3. Introduction

 

Assignment 0

2

2/29*

3

3/7

1. Introduction

2. Logic Simulation

 

Assignment 1

4

3/14

1. Logic Simulation

2. Fault Modeling

 

Assignment 2

5

3/21

1. Fault Modeling

6

3/28

1. Fault Modeling

2. Fault Simulation

 

Assignment 3

7

4/4*

8

4/11

1. Fault Simulation

2. Comb_ATPG

 

Assignment 4

9

4/18

1. Comb_ATPG

2. Testability

 

Assignment 5

10

4/25

Midterm

11

5/2

1. Testability

2. seq_ATPG

12

5/9

1. seq_ATPG

2. DFT

 

Assignment 6

13

5/16

1. DFT

2.Test Compression

14

5/23

1. Lab1

2. Lab2

15

5/30

1.BIST

2.Test Compression

16

6/6

1.Test Compression

2.memory testing

17

6/13

Final Examination