UEE 1306

Logic Design

Schedule

Tuesday 10:10am-12:00am and Friday 13:20pm-14:10pm
Week	Date	Time	Lecture	Practices	Quiz
1	9/24	5	Class introduction
2	9/28	34	Number Systems and Conversion	ch1 : 4, 5, 7, 19, 28, 39, 44 TA: 林晉寬(ch1)	Quiz_1
	10/1	5
3	10/5	34	Boolean Algebra	ch2 : 5, 6, 13, 18, 21, 29 TA: 吳佩穎(ch2)	Quiz_2
	10/8	5
4	10/12	34	Boolean Algebra(Cont'd)	ch3 : 6, 7, 12, 21, 24 TA: 吳佩穎(ch3)	Quiz_3
	10/15	5
5	10/19	34	Minterm and Maxterm Expansions	ch4 : 1, 6, 8, 13, 29, 40 TA: 林晉寬(ch4)	Quiz_4
	10/22	5
6	10/26	34	Karnaugh Maps	ch5 : 3, 4, 6, 9, 28 TA: 林振岡(ch5)	Quiz_5
	10/29	5
7	11/2	34	Multi-Level Gate Circuits	ch7 : 1, 4, 8 ,10, 29 TA: 林晉寬(ch7)	Quiz_7
	11/5	5
8	11/9	34	Combinational Circuit Design Simulation	ch8 : 6, 9, 12, 14, A TA: 吳佩穎(ch8)	Quiz_8
	11/12	5
9	11/16	34	Midterm	ch9 : 1, 4, 6, 10, 19, 36 TA: 林振岡(ch9)	Quiz_9
	11/19	5	Multiplexers, Decoders, and Programming Logic Devices (PLDs)
10	11/23	34	Latches and Flip-Flops	ch11 : 1, 3, 8, 9, 10, 25 TA: 林振岡(ch11)	Quiz_11
	11/26	5
11	11/30	34	Registers and Counters	ch12 : 1, 6, 8, 13, 29, 40 TA: 吳佩穎(ch12)	Quiz_12
	12/3	5
12	12/7	34	Analysis of Clocked Sequential Circuits	ch13 : 3, 4, 12, 21 TA: 林晉寬(ch13)	Quiz_13
	12/10	5
13	12/14	34	Derivation of State Graphs and Tables	ch14 : 5, 10, 13, 23, 26, 33, 38 TA: 吳佩穎(ch14)	Quiz_14
	12/17	5
14	12/21	34	Reduction of State Tables	ch15 : 1, 3, 6, 9, 12, 40 TA: 林振岡(ch15)
	12/24	5
15	12/28	34	Sequential Circuit Design	ch16 : 16, 17, 18, 22 TA: 林晉寬(ch16)
	12/31	5	Holiday
16	1/4	34	Flexibly adjusted
	1/7	5
17	1/11	34	Final (1/11)
	1/14	5